<> <http://www.w3.org/2000/01/rdf-schema#comment> "The repository administrator has not yet configured an RDF license."^^<http://www.w3.org/2001/XMLSchema#string> .
<> <http://xmlns.com/foaf/0.1/primaryTopic> <http://digilib.unila.ac.id/id/eprint/87540> .
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<http://digilib.unila.ac.id/id/eprint/87540> <http://purl.org/dc/terms/title> "GENERATOR SET UJI UNTUK DIAGNOSIS KESALAHAN\r\nRANGKAIAN KOMBINASIONAL MULTIPLEXER 4 LINE TO\r\n1 LINE MENGGUNAKAN METODE ARTIFICIAL NEURAL\r\n\r\nNETWORK"^^<http://www.w3.org/2001/XMLSchema#string> .
<http://digilib.unila.ac.id/id/eprint/87540> <http://purl.org/ontology/bibo/abstract> "An integrated circuit (IC) is built, among other things, using combinational digital\r\ncircuits. Large-scale IC production requires a method for testing using sampling\r\nmethods at specific time intervals. One method involves using a set-test generator.\r\nA set-test generator is built to detect errors in combinational digital circuits. In\r\nprevious research, the set-test generator was made using an arrangement of\r\nelectronic circuits. Each change in the test circuit required changes in the electronic\r\ncircuits of the set-test generator, which influenced, among other things, the cost of\r\n\r\nsystem development. This research developed a set-test generator using a software-\r\nbased neural network method. Therefore, if the input and output are within the\r\n\r\nscope of the microcontroller, any changes in the test circuit only require changes to\r\nthe neural network model, directly impacting cost-efficiency in system\r\ndevelopment. As a result, this research has built a set-test generator system capable\r\nof accurately detecting error locations. The model's accuracy reaches 99.95%,\r\nmaking the prediction results of the model highly accurate. In addition to detecting\r\nsingle errors, the set-test circuit can also accurately detect double and triple error\r\nlocations chosen.\r\n\r\nKeywords: set-test generator, neural network, single error, multiple error, test\r\n\r\ncircuit.Integrated circuit (IC) dibangun salah satunya menggunakan rangkaian digital\r\nkombinasional. Produksi IC dalam skala besar membutuhkan sebuah metode untuk\r\nmelakukan pengujian dengan metode sampling dalam satuan waktu tertentu. Salah\r\nsatunya menggunakan alat generator set uji. Generator set uji dibangun untuk\r\nmelakukan pendeteksian kesalahan pada rangkaian digital kombinasional. Pada\r\npenelitian sebelumnya, generator set uji dibuat menggunakan susunan rangkaian\r\nelektronika. Setiap perubahan rangkaian uji membutuhkan perubahan rangkaian\r\nelektronika pada generator set uji. Sehingga berpengaruh salah satunya pada\r\nbesarnya cost dalam pembuatan sistem. Penelitian ini membangun sebuah generator\r\nset uji dengan menggunakan metode neural network berbasis software. Sehingga\r\napabila input dan output dalam cakupan mikrokontroler setiap perubahan rangkaian\r\nuji hanya dilakukan perubahan model neural network yang berdampak langsung\r\npada cost pembangunan sistem yang lebih hemat. Hasilnya pada penelitian ini telah\r\nterbangun sistem generator set uji yang mampu mendeteksi lokasi kesalahan\r\ndengan tepat. Akurasi model mencapai 99,95 % membuat hasil prediksi dari model\r\nyang dibuat akurat. Selain dapat mendeteksi kesalahan tunggal, rangkaian set uji\r\njuga dapat melakukan pendeteksian kesalahan jamak ganda dan tiga lokasi\r\nkesalahan yang dipilih dengan akurat.\r\n\r\nKata Kunci: Generator set uji, neural network, kesalahan tunggal, kesalahan\r\n\r\njamak, rangkaian uji"^^<http://www.w3.org/2001/XMLSchema#string> .
<http://digilib.unila.ac.id/id/eprint/87540> <http://purl.org/dc/terms/date> "2024-08-06" .
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